Fault Modeling
In my Testing Digital Logic class, we are learning about “fault modeling,” which is the study of ways that integrated-circuit chip defects can be mathematically represented.
I’m thinking that it would be so cool if that worked for me! It would be great if there were a way to determine a mathematical model that is an accurate representation of myself. Then I could analyze my faults in a quantitative way and correct them systematically. Essentially, I could become an ideal Jed in a finite amount of time.
Unfortunately, this is currently an impossibility due to processing-power limitations (in my case, the number of faults is astronomical).
Perhaps this can be the topic of my Ph.D. thesis.
Posted: January 29th, 2008 under Thoughts.
Comments
Comment from Josiah
Time 2008/01/30 at 4:26 pm
According to Steven Wolfram, such a model would be possible — if not with Mathematical formulae — certainly with a computational algorithm.
“When we find the human genome, we’re kind of finding the raw bits of the machine code for the system.” he says — “But perhaps we can find a map for the algorithms. Some kind of “algomap” that shows us the different overall rules…”
See, it’s really quite simple! 
Comment from Jed
Time 2008/01/31 at 5:00 pm
Haha… oh that Stephen Wolfram! What grandiose scheme will he think up next?!?
Comment from Marty
Time 2008/01/29 at 9:27 pm
Maybe the number of faults isn’t the problem. You just need to plug into a higher Power Source that can handle the load……. : )